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a soundport controller ad1812 features compatibility with: sound blaster pro* adlib* windows* sound system 16-bit sd stereo codec mpc level-2+ mixer dual dma/full duplex operation on-chip fifo buffers sample rates from 5.5 khz to 50 khz adpcm compression/decompression plug and play compliant compatible midi mpu-401 port integrated game port free supporting software: windows 3.1 driver windows 95 driver control applets diagnostics power management modes operation from +5 v supply 16-bit parallel interface to isa bus 24 ma bus drive capability * sound blaster pro is a trademark of creative labs, ltd. * adlib is a trademark of adlib multimedia. * windows is a trademark and microsoft is a registered trademark of * microsoft corp. soundport is a registered trademark of analog devices, inc. product overview the ad1812 soundport? controller is a single chip audio sub- system for adding 16-bit stereo audio to personal computers. the ad1812 is compatible with sound blaster pro, adlib, and the microsoft* windows sound system. the ad1812 provides an integrated audio solution for enhanced business audio, enter- tainment sound effects, and multimedia applications. the ad1812 audio subsystem combines an integrated digital audio controller, a powerful signal processor, a mixer, and a 16-bit sd stereo codec. the dos games register set, the win- dows sound system register set, music synthesis hardware, an mpu-401 compatible uart interface, a game port (with timer), and a plug and play isa interface are all contained on chip. the on-chip plug and play (pnp) routine provides con- figuration services for the internal logical devices and an exter- nal modem chipset. the ad1812 can record compress and playback voice, sound and music. the system provides all pc 95 audio conversion and compatibility requirements for a multimedia enabled pc. ( continued on page 12) functional block diagram 0db/ 20db g m g m g m m s g g m m s s s selector s s s s d d/a converter attn/ mute s d a/d converter pga digital mix attenuate s s format fifo format fifo game register set & wss register set midi_in mpu-401 uart joystic k/game port interface midi _out a_1 b_1 a_x b_x a_2 b_2 a_y b_y xtali/o parallel bus interface control registers plug and play registers attn s d d/a converter adsp-2171 rom ram mic line aux1 l_out mono i/o r_out mono_in aux2 dacin dacout drq (0, 1, 3, 5, 6, 7) irq (3, 4, 5, 7, 9, 10, 11, 12) pc_d (15:0) pc_a (15:0) aen dack (0, 1, 3, 5, 6, 7) ior iow sbhe io_ch16 pwrdwn pnp ad1812 modem_irq modem_sel g = gain/amplifier block m = mute block oscillators rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. ? analog devices, inc., 1996 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703
rev. 0 C2C ad1812Cspecifications standard test conditions unless otherwise noted dac test condition s temperature 0 c calibrated digital supply (v dd ) 5.0 v 0 db attenuation analog supply (v cc ) 5.0 v input full scale 16-bit linear mode sample rate (f s ) 48 khz 10 k w output load input signal 1008 hz mute off analog output passband 20 hz to 20 khz adc test conditions v ih 2.0 v calibrated 0 db gain v il 0.8 v input C1.0 db relative to full scale v oh 2.4 v line input selected v ol 0.4 v 16-bit linear mode analog input parameter min typ max units input voltage (rms values assume sine wave input) line, aux1, mono_in, aux2, dacin 1 v rms 2.55 2.83 3.11 v p-p mic with +20 db gain (mge = 1) 0.1 v rms 0.250 0.283 0.316 v p-p mic with 0 db gain (mge = 0) 1 v rms 2.55 2.83 3.11 v p-p input impedance* 10 17 k w input capacitance* 15 pf programmable gain amplifieradc parameter min typ max units step size (0 db to 22.5 db) 1.3 1.5 1.7 db (all steps tested) pga gain range span 21.5 22.5 23.5 db auxiliary, line, microphone and mono input analog gain/amplifiers/attenuators parameter min typ max units step size: aux1, aux2, dacin, line, mic (all steps tested) (+12 db to C30 db) 1.25 1.5 1.75 db (C31.5 db to C34.5 db) 1 1.5 2.0 db input gain/attenuation range: aux1, aux2, dacin, line, mic 45.0 46.5 47.5 db step size: mono_in (all steps tested) (0 db to C39 db) 2.5 3.0 3.6 db (C42 db to C45 db) 2.2 3.0 3.85 db input gain/attenuation range: mono_in 43 45 46 db digital decimation and interpolation filters* parameter min typ max units passband 0 0.4 f s hz passband ripple 0.1 db transition band 0.4 f s 0.6 f s hz stopband 0.6 f s hz stopband rejection 74 db group delay 15/f s sec group delay variation over passband 0.0 m s *guaranteed not tested. specifications subject to change without notice.
analog-to-digital converters parameter min typ max units resolution 16 bits dynamic range (C60 db input thd+n referenced to full scale, 80 86 db a-weighted) thd+n (referenced to full scale) 0.02 % C78 C74 db signal-to-intermodulation distortion* (ccif method) 80 db adc crosstalk* line inputs (input l, ground r, read r; input r, ground l, read l) C90 C80 db line to mic (input line, ground and select mic, read adc) C90 C80 db line to aux1 C90 C80 db line to aux2 C90 C80 db gain error (full-scale span relative to nominal input voltage) 10 % interchannel gain mismatch (difference of gain errors) 0.5 db adc offset error 10 mv digital-to-analog converters parameter min typ max units resolution 16 bits dyna mic range (C60 db input thd+n referenced to full scale, 74 81 db a-weighted) thd+n (referenced to full scale) 0.022 % C77 C73 db signal-to-intermodulation distortion* (ccif method) 90 db gain error (full-scale span relative to nominal input voltage) 15 % interchannel gain mismatch (difference of gain errors) 0.5 db dac crosstalk* (input l, zero r, measure r_out; input r, C90 C80 db zero l, measure l_out) total out-of-band energy (measured from 0.6 f s to 100 khz)* C60 db audible out-of-band energy (measured from 0.6 f s to 20 khz)* C70 db dac attenuator parameter min typ max units step size (0 db to C22.5 db) 1.3 1.5 1.7 db step size (C22.5 db to C94.5 db)* 1.0 1.5 2.0 db output attenuation range span* 93.5 94.5 95.5 db mute attenuation of 0 db fundamental* 80 db digital mix attenuator parameter min typ max units step size (0 db to C22.5 db) 1.3 1.5 1.7 db step size (C22.5 db to C94.5 db)* 1.0 1.5 2.0 db digital mix attenuation range span* 93.5 94.5 95.5 db *guaranteed not tested. specifications subject to change without notice. ad1812 rev. 0 C3C
ad1812 rev. 0 C4C analog output parameter min typ max units full-scale output voltage o l = 0 1.8 2.0 2.2 v p-p o l = 1 2.5 2.8 3.11 v p-p output impedance* 600 w external load impedance 10 k w output capacitance* 15 pf external load capacitance 100 pf v ref 2.05 2.25 2.45 v v ref output impedance 4 k w mute click (muted output minus unmuted midscale dac output)* 5mv system specifications parameter min typ max units system frequency response ripple* (line in to line out) 1.0 db differential nonlinearity* 1 lsb phase linearity deviation* 5 degrees static digital specifications parameter min typ max units high-level input voltage (v ih ): digital inputs 2 v low-level input voltage (v il ) 0.8 v high-level output voltage (v oh ), i oh = 24 ma 2.4 v low-level output voltage (v ol ), i ol = 24 ma 0.4 v input leakage current C10 10 m a output leakage current C10 10 m a power supply parameter min typ max units power supply rangeanalog 4.75 5.25 v power supply rangedigital 4.75 5.25 v power supply current 250 ma power dissipation 1.25 w analog supply current 55 ma digital supply current 195 ma digital power supply currentpower down 15 ma analog power supply currentpower down 1 ma power supply rejection (100 mv p-p signal @ 1 khz)* (at both analog and digital supply pins, both adcs and dacs) 40 db clock specifications* parameter min typ max units input clock frequency 6 14.31818 18 mhz recommended clock duty cycle 10 50 90 % power up initialization time 500 ms *guaranteed not tested. specifications subject to change without notice.
ad1812 rev. 0 C5C timing parameters (guaranteed over operating temperature range) parameter symbol min typ max units iow / ior strobe width t stw 100 ns iow / ior rising to iow / ior falling t bwdn 80 ns write data setup to iow rising t wdsu 10 ns ior falling to valid read data t rddv 40 ns aen setup to iow / ior falling t aesu 10 ns aen hold from iow / ior rising t aehd 0ns adr setup to iow / ior falling t adsu 10 ns adr hold from iow / ior rising t adhd 10 ns dack rising to iow / ior falling t dksu1 20 ns iow / ior rising to dack falling t dkhd1 0ns dack setup to iow / ior falling t dksu2 10 ns data hold from ior rising t dhd1 20 ns data hold from iow rising t dhd2 15 ns drq hold from iow / ior falling t drhd 25 ns dack hold from iow rising t dkhd2 10 ns dack hold from ior rising t dkhd3 10 ns *guaranteed, not tested. specifications subject to change without notice. general notes use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an additional device, the values given in this data sheet reflect statistical variations and worst cases. consequently, you cannot meaningfully add up parameters to derive longer times. note that all 8-bit dma transfers occur on channels 0, 1, and 3, while all 16-bit dma transfers occur on channels 5, 6, and 7. t dksu1 t dkhd1 t aesu t aehd t stw t rddv t dhd1 t adhd t adsu drq (0, 1, 3, 5, 6, 7) dack (0, 1, 3, 5, 6, 7) aen ior pc_d (7:0) / pc_d (15:0) pc_a (15:0) figure 1. pio read cycle t dkhd3 t aesu t aehd t rddv t dhd1 t dksu2 t drhd drq (0, 1, 3, 5, 6, 7) dack (0, 1, 3, 5, 6, 7) aen ior pc_d (7:0) / pc_d (15:0) t stw figure 3. dma read cycle t dksu1 t dkhd1 t aesu t aehd t stw t dhd2 t adhd drq (0, 1, 3, 5, 6, 7) dack (0, 1, 3, 5, 6, 7) aen iow pc_d (7:0) / pc_d (15:0) pc_a (15:0) t adsu t wdsu figure 2. pio write cycle t dkhd2 t aesu t aehd t dhd2 t dksu2 t drhd drq (0, 1, 3, 5, 6, 7) dack (0, 1, 3, 5, 6, 7) aen iow pc_d (7:0) / pc_d (15:0) t stw t wdsu figure 4. dma write cycle
ad1812 rev. 0 C6C format word 1 (16-bit) word 0 (16-bit) msb lsb msb lsb mono, 16-bit upper 8 bits of lower 8 bits of upper 8 bits of lower 8 bits of sample 1 sample 1 sample 0 sample 0 little endian left channel left channel left channel left channel stereo, 16-bit upper 8 bits of lower 8 bits of upper 8 bits of lower 8 bits of sample 0 sample 0 sample 0 sample 0 little endian right channel right channel left channel left channel mono, 8-bit sample 3, 8 bits sample 2, 8 bits sample 1, 8 bits sample 0, 8 bits linear pcm m -law pcm left channel left channel left channel left channel a-law pcm stereo, 8-bit sample 1, 8 bits sample 1, 8 bits sample 0, 8 bits sample 0, 8 bits linear pcm m -law pcm right channel left channel right channel left channel a-law pcm mono, 4-bit sample 7, sample 6, sample 5, sample 4, sample 3, sample 2, sample 1, sample 0, 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits ima-adpcm left left left left left left left left channel channel channel channel channel channel channel channel stereo, 4-bit sample 3, sample 3, sample 2, sample 2, sample 1, sample 1, sample 0, sample 0, 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits ima-adpcm right left right left right left right left channel channel channel channel channel channel channel channel mono, 16-bit lower 8 bits of upper 8 bits of lower 8 bits of upper 8 bits of sample 1 sample 1 sample 0 sample 0 big endian left channel left channel left channel left channel stereo, 16-bi t lower 8 bits of upper 8 bits of lower 8 bits of upper 8 bits of sample 0 sample 0 sample 0 sample 0 big endian right channel right channel left channel left channel *regardless of the data format used, the ad1812s codec always transfers 32 bits of data (two 16-bit words). table i. codec transfer 16-bit interface, no byte swap (p/cinf8 = 0, p/cbsw = 0)* ior/iow t bwdn word 0 word 1 t stw t stw data (15:0) figure 5. codec transfers 16-bit interface
ad1812 rev. 0 C7C table ii. codec transfer 16-bit interface with byte swap (p/cinf8 = 0, p/cbsw = 1)* format word 1 (16-bit) word 0 (16-bit) msb lsb msb lsb mono, 16-bit lower 8 bits of upper 8 bits of lower 8 bits of upper 8 bits of sample 1 sample 1 sample 0 sample 0 little endian left channel left channel left channel left channel stereo, 16-bit lower 8 bits of upper 8 bits of lower 8 bits of upper 8 bits of sample 0 sample 0 sample 0 sample 0 little endian right channel right channel left channel left channel mono, 8-bit sample 2, 8 bits sample 3, 8 bits sample 0, 8 bits sample 1, 8 bits linear pcm m -law pcm a-law pcm left channel left channel left channel left channel stereo, 8-bit sample 1, 8 bits sample 1, 8 bits sample 0, 8 bits sample 0, 8 bits linear pcm m -law pcm a-law pcm left channel right channel left channel right channel mono, 4-bit sample 5, sample 4, sample 7, sample 6, sample 1, sample 0, sample 3, sample 2, 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits ima-adpcm left left left left left left left left channel channel channel channel channel channel channel channel stereo, 4-bit sample 2, sample 2, sample 3, sample 3, sample 0, sample 0, sample 1, sample 1, 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits ima-adpcm right left right left right left right left channel channel channel channel channel channel channel channel mono, 16-bit upper 8 bits of lower 8 bits of upper 8 bits of lower 8 bits of sample 1 sample 1 sample 0 sample 0 big endian left channel left channel left channel left channel stereo, 16-bi t upper 8 bits of lower 8 bits of upper 8 bits of lower 8 bits of sample 0 sample 0 sample 0 sample 0 big endian right channel right channel left channel left channel *regardless of the data format used, the ad1812s codec always transfers 32 bits of data (two 16-bit words). ior/iow t bwdn word 0 word 1 t stw t stw data (15:0) figure 6. codec transfers 16-bit interface
ad1812 rev. 0 C8C table iii. codec transfer 8-bit interface (p/cinf8 = 1)* format byte 3 byte 2 byte 1 byte 0 msb lsb msb lsb msb lsb msb lsb mono, 16-bit upper 8 bits of lower 8 bits of upper 8 bits of lower 8 bits of sample 1 sample 1 sample 0 sample 0 little endian left channel left channel left channel left channel stereo, 16-bit upper 8 bits of lower 8 bits of upper 8 bits of lower 8 bits of sample 0 sample 0 sample 0 sample 0 little endian right channel right channel left channel left channel mono, 8-bit sample 3, 8 bits sample 2, 8 bits sample 1, 8 bits sample 0, 8 bits linear pcm m -law pcm left channel left channel left channel left channel a-law pcm stereo, 8-bit sample 1, 8 bits sample 1, 8 bits sample 0, 8 bits sample 0, 8 bits linear pcm m -law pcm right channel left channel right channel left channel a-law pcm mono, 4-bit sample 7, sample 6, sample 5, sample 4, sample 3, sample 2, sample 1, sample 0, 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits ima-adpcm left left left left left left left left channel channel channel channel channel channel channel channel stereo, 4-bit sample 3, sample 3, sample 2, sample 2, sample 1, sample 1, sample 0, sample 0, 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits ima-adpcm right left right left right left right left channel channel channel channel channel channel channel channel mono, 16-bit lower 8 bits of upper 8 bits of lower 8 bits of upper 8 bits of sample 1 sample 1 sample 0 sample 0 big endian left channel left channel left channel left channel stereo, 16-bi t lower 8 bits of upper 8 bits of lower 8 bits of upper 8 bits of sample 0 sample 0 sample 0 sample 0 big endian right channel right channel left channel left channel *regardless of the data format used, the ad1812s codec always transfers 32 bits of data (two 16-bit words). ior/iow t bwdn byte 0 data (7:0) byte 1 byte 2 byte 3 left sample right sample figure 7. codec transfers 8-bit interface
ad1812 rev. 0 C9C absolute maximum ratings* parameter min max units power supplies digital (v dd ) C0.3 6.0 v analog (v cc ) C0.3 6.0 v input current (except supply pins) 10.0 ma analog input voltage (signal pins) C0.3 v cc + 0.3 v digital input voltage (signal pins) C0.3 v dd + 0.3 v ambient temperature (operating) 0 +70 c storage temperature C65 +150 c *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide temperature package package model range description option ad1812js 0 c to +70 c 160-lead pqfp s-160 AD1812JST 0 c to +70 c 160-lead tqfp st-160 warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad1812 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. pqfp and tqfp pin locations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 71 72 73 74 75 76 77 78 79 80 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 pin 1 identifier top view pins down (not to scale) ad1812 nc reset modem_sel gndd v dd irq3 irq4 irq5 irq7 irq9 irq10 irq11 irq12 gndd v dd gndd v dd drq0 drq1 nc drq3 drq5 drq6 drq7 ioch16 midi_out xctl0 v dd gndd gndd v dd gndd dack0 dack1 dack3 dack5 dack6 dack7 gndd gndd nc nc nc nc gndd v dd sbhe pc_a15 pc_a14 pc_a13 pc_a12 pc_a11 pc_a10 pc_a9 pc_a8 ior gndd v dd gndd pc_a7 pc_a6 pc_a5 pc_a4 pc_a3 pc_a2 pc_a1 pc_a0 v dd xtali xtalo midi_in aen iow gndd reset pwrdwn pnp modem_irq modem_en gvc nc = no connect nc nc nc v dd pc_d3 pc_d4 pc_d5 gndd v dd pc_d6 pc_d7 pc_d8 gndd v dd pc_d9 pc_d10 pc_d11 gndd v dd pc_d13 pc_d14 pc_d12 pc_d15 nc nc gndd v dd nc nc nc gndd gndd v dd gndd v dd pc_d0 pc_d1 pc_d2 xctl1 nc gndg v ddg v cc a_x a_y b_x b_y gnda l_filt r_filt l_line r_line l_mic r_mic b_2 vref_x v cc vref a_2 b_1 gnda r_aux1 l_aux1 l_aux2 r_aux2 r_monoin l_out r_out l_monoin v cc mono_in gnda m_out r_dacout r_dacin l_dacin l_dacout adgnd advdd a_1
ad1812 rev. 0 C10C pin description parallel interface pin name p/tqfp i/o description pc_d[15:0] 128C131, 136C139, i/o isa bus pc data. pc_d15 to pc_d8 in conjunction with an active hi 142C145, 150C153 sbhe connects the ad1812 to the high byte data on the bus, while pc_d7 to pc_d0 connects to the low byte data on the bus. irq(x) 108C115 o interrupt request. irq (3, 4, 5, 7, 9, 10, 11, 12). active hi signals indicating a pending interrupt. drq(x) 98C103 o dma request. drq (0, 1, 3, 5, 6, 7). active hi signals indicating a request for dma bus operation. drq0, drq1 and drq3 request 8-bit dma operations while drq5, drq6 and drq7 request 16-bit operations. pc_a[15:0] 8C15, 18C25 i isa bus pc address. connects the ad1812 to the isa bus address lines. aen 32 i address enable. active hi signal indicates dma transfer. active lo signal indicates pio transfer. dack (x) 84C85, 87C90 i dma acknowledge. dack (0, 1, 3, 5, 6, 7). active lo signal indicating that a dma operation can begin. ior 26 i i/o read indicates a read operation. iow 33 i i/o write indicates a write operation. sbhe 7 i system byte high enable. active lo signal that indicates a byte is being trans- ferred on the upper byte of the 16-bit bus. ioch16 97 o io channel 16. active lo signal indicating that one of the logical devices inside the ad1812 is decoded as a 16-bit device. reset 35 i reset. active hi. reset 119 i inverted reset. active lo. analog signals pin name p/tqfp i/o description l_line 56 i left line-level input. r_line 55 i right line-level input. l_mic 58 i left microphone input. r_mic 57 i right microphone input. l_aux1 64 i left auxiliary #1 line-level input. also used for cd input. r_aux1 63 i right auxiliary #1 line-level input. also used for cd input. l_aux2 66 i left auxiliary #2 line-level input. also used for a wavetable input. r_aux2 65 i right auxiliary #2 line-level input. also used for a wavetable input. l_out 69 o left line-level output. left channel post-mixed output. r_out 68 o right line-level output. right channel post-mixed output. mono_in 71 i mono input. m_out 73 o mono output. sum of l_out and r_out. l_dacout 78 o left dac out. left channel games audio output. r_dacout 75 o right dac out. right channel games audio output. l_dacin 77 i left dac in. when coupled to l_dacout, allows mixing of left channel games audio with left channel audio converted by the codec. the post-mixed output is avail- able on l_out. r_dacin 76 i right dac in. when coupled to r_dacout, allows mixing of right channel games audio with right channel audio converted by the codec. the post-mixed output is available on r_out. l_monoin 70 i left mono in. when coupled to l_out, m_out reflects the left post-mixed output. r_monoin 67 i right mono in. when coupled to r_out, m_out reflects the right post-mixed output.
ad1812 rev. 0 C11C modem interface signals pin name p/tqfp i/o description modem_irq 38 i modem irq. the external modem asserts this pin hi to indicate a pending inter- rupt. the ad1812 converts this signal to the appropriate interrupt in either plug and play (ldn = 5) or non-plug and play mode. modem_en 39 i modem enable. when this pin is asserted (hi), the ad1812 enables the logical device (ldn = 5) for an external modem chipset. otherwise, ldn = 5 does not exist. the state of this pin should not be altered after reset. modem_sel 118 o modem select. this active lo pin is a chip select for an external modem chipset. the ad1812 decodes the (plug & play or non-plug and play) configured isa bus address. aen must be lo before asserting the modem_sel pin. game port pin name p/tqfp i/o description a_1 41 i game port a, button #1. a_2 42 i game port a, button #2. a_x 46 i game port a x-axis. a_y 47 i game port a y-axis. b_1 43 i game port b, button #1. b_2 44 i game port b, button #2. b_x 48 i game port b x-axis. b_y 49 i game port b y-axis. midi interface signals pin name p/tqfp i/o description midi_in 31 i rxd midi input. midi_out 96 o txd midi output. miscellaneous pin name p/tqfp i/o description pnp 37 i plug and play select. when this pin is asserted (hi), the plug and play mode is enabled. if pnp is lo, the ad1812 operates in legacy mode, and the plug and play configuration is disabled. xtalo 30 o 14.31818 mhz crystal output. xtali 29 i 14.31818 mhz clock input, can be osc from the isa bus. pwrdwn 36 i power down signal. active lo. vref_x 60 o voltage reference. vref 59 i voltage reference filter. l_filt 54 i left channel filter input. r_filt 53 i right channel filter input. xctl0 95 o external control 0. the state of this pin (ttl hi or lo) is reflected in codec indexed register 0x0a, bit 6. xctl1 159 o external control 1. the state of this pin (ttl hi or lo) is reflected in codec indexed register 0x0a, bit 7. gvc 40 i game port voltage capacitor. nc 1C4, 81, 120C125, no connect. 156C158, 160
ad1812 rev. 0 C12C power supplies pin name p/tqfp i/o description v cc 51, 61, 72 i analog supply voltage (+5 v). gnda 52, 62, 74 i analog ground. v dd 6, 17, 28, 91, i digital supply voltage (+5 v). 94, 104, 107, 116, 126, 132, 135, 140, 146, 149, 154 gndd 5, 16, 27, 34, 82, i digital ground. 83, 86, 92, 93, 105, 106, 117, 127, 133, 134, 141, 147, 148, 155 advdd 80 i analog/digital supply voltage. connect to +5 v cc . adgnd 79 i analog/digital ground. connect to analog ground plane. v ddg 50 i game port digital voltage supply. connect to +5 v dd . gndg 45 i game port digital ground. connect to the digital ground plane. ( continued from page 1 ) host pc interface all necessary isa bus interface logic is completely contained on- chip. this includes address decoding for all onboard resources, control and signal interpretation, dma selection and control logic, irq selection and control logic, and all interface configu- ration logic (see table iv). the ad1812 supports a dma request/grant architecture for transferring data with the isa bus. one, two, or three dma channels can be supported. programmed i/o (pio) mode is also supported for control register accesses and for applications lacking dma control. the ad1812 includes dual dma count registers for full-duplex operation enabling simultaneous capture and playback on separate dma channels. the ad1812 is fully configurable according to the plug and play isa specification. in a non-plug and play environment, the built in plug and play protocol can be disabled. when plug and play is disabled, the ad1812 operates under a fixed address space. table iv. emulated logical devices logical pnp device emulated compatible number device device 0 windows sound system 1 sound blaster pro v. 2.01 pnpb002 2 opl3 music synthesizer pnpb020 3 midi mpu-401 port pnpb006 4 game/joystick port pnpb02f 5* modem pnp0501 *if modem_en is asserted. wss compatible codec the ad1812 contains the ad1845 soundport stereo codec for business audio support and multimedia applications. the codec includes stereo audio converters, complete on-chip filtering, mpc level-2 compliant analog mixing, programmable gain and attenuation, a variable sample frequency generator, and fifos buffering the isa bus. the codec includes a stereo pair of ?d analog-to-digital con- verters and a stereo pair of ?d digital-to-analog converters. in- puts to the adc can be selected from four stereo pairs of analog signals: line (line), microphone (mic), auxiliary line #1 (aux1), and post-mixed dac output. in addition, an analog mixer allows a mono input (mono_in), mic, aux1, line and auxiliary line #2 (aux2) to be mixed with the dacs out- put. a software-controlled programmable gain stage allows in- dependent gain for each channel going into the adc. the adcs output can be digitally mixed with the dacs input. the pair of 16-bit outputs from the adcs are available over a 16-bit bidirectional interface that also supports 16-bit digital in- put to the dacs and control information. the codec can accept and generate 16-bit twos-complement pcm linear (big endian or little endian) digital data, 4-bit ima-adpcm compatible digital data, 8-bit unsigned magnitude pcm linear data, and 8-bit m -law or a-law companded digital data. the ad1812 includes a variable sample frequency generator, which allows the codec to instantaneously change sample rates from 5.5 khz to 50 khz with a resolution of 1 hz. this is a su- perb way to create special audio effects.
ad1812 rev. 0 C13C table v. plug and play registers (pnp asserted) port name location type address 0x279 (printer status port) write-only write_data 0xa79 (printer status port + 0x800) write-only read_data relocatable in range 0x203 C 0x3ff read-only table vi. non-plug and play registers (pnp deasserted) port name location type address 0x234 write-only write_data 0x235 write-only read_data relocatable in range 0x203 C 0x3ff read-only pnp ad1812 (card) status for cards in pnp mode (pnp_enable asserted), the plug and play isa specification describes how to transfer the ad1812 from its start-up state, wait for key state, to the configura- tion state, config state. in the configuration state, the i/o ranges, interrupt channels, and dma channels can be assigned. for non-pnp operation, no initialization protocol is needed because the card is locked in the configuration state. configuration register description the following describes only the subset of pnp registers that are unique to the ad1812 or necessary for non-pnp operation. all other pnp registers are described in the plug and play isa specification. a register is selected by performing an 8-bit i/o write to the address port, followed by either a read from the read_data loca tion or a write to the write_data location. successive reads or writes to a single register can be done without rewriting the address register. the following are valid values for the address port. table vii. pnp address port registers address register name value type description rd_data port 0x00 write-only sets the value of the read_data port. config control 0x02 write-only r esets all logical de vices. logical device 0x07 read/write selects current logical number device. powerdown 0x20 read/write manages power for portions of the ad1812. sound blaster emulation sound blaster emulation is provided using a combination of the embedded signal processor and dedicated hardware. all sound blaster pro version 2.01 functions are supported including record. the hardware registers are fully implemented within the ad1812, and the internal signal processor executes a command controller to interpret all commands. the ad1812 uses the in- ternal signal processor for decoding compressed files compatible with sound blaster adpcm. music synthesizer emulation the ad1812 includes an embedded signal processor based on analog devices 16-bit fixed-point digital signal processor fam- ily. all dsp instructions are rom coded internally. the music synthesis algorithm running on the signal processor emu- lates the functions of industry standard opl3 fm synthesizer chips and delivers 20 voice polyphony. a dedicated pair of ?d dacs converts the digitally synthesized music before mixing with the ad1812 codec line output. eusynth-1+ was developed by euphonics, a research and prod- uct development company that specializes in audio processing and electronic music synthesis. mpu-401 interface the primary interface for communicating midi data to and from the host pc is the emulated mpu-401 interface. the mpu-401 interface includes has a built-in fifo for communi- cating to the host bus. game port interface an ibm-compatible game port interface is provided on-chip. the game port is capable of supporting up to two joysticks. connecting the game port to a 15-pin d-sub connector requires only a few capacitors and resistors. the ad1812 includes a built-in game port timer. modem interface asserting the modem_en pin on the ad1812 provides chip select, interrupt handling and address decoding for an external modem chipset. the ad1812 decodes the modem isa bus address and issues a modem select on the modem_sel pin. interrupts generated by the external modem are handled on the modem_irq pin, converted to the assigned system interrupt by the ad1812, and posted to the isa bus. the modem inter- face operates in a pnp or non-pnp enabled system. plug and play (pnp) the ad1812 can be used under pnp control or in a non-pnp mode. the non-pnp registers mimic the pnp register set, ex- cept for the user defined addresses for the pnp address and write_data registers. the pnp registers are selected by asserting the pnp pin. with the pnp pin deasserted, the non-pnp registers are selected. eusynth-1+
ad1812 rev. 0 C14C table viii. windows sound system, logical device number = 0 register name address type description value activate 0x30 read/write activates device. i/o range check 0x31 read/write performs conflict check on selected i/o range. i/o port base 0x60 read/write i/o base [15:8]. address 0x61 read/write i/o base [7:0]. irq level select 0x70 read/write selects interrupt level. irq type select 0x71 read-only active hi, level-sensitive (not user programmable). dma select 0 0x74 read/write indicates dma capture channel. dma select 1 0x75 read/write i ndicates dma playback channel. (if dma 0 is not used, capture and playback occurs on dma 1.) table ix. game registers, logical device number = 1 address register name value type description activate 0x30 read/write activates device. i/o range check 0x31 read/write performs conflict check on selected i/o range. i/o port base 0x60 read/write i/o base [9:8]. address 0x61 read/write i/o base [7:0]. irq level select 0x70 read/write selects interrupt level. irq type select 0x71 read-only active hi, edge-sensitive (not user programmable). dma select 0 0x74 read/write indicates which 8-bit dma channel. table x. music synthesizer, logical device number = 2 address register name value type description activate 0x30 read/write activates device. i/o range check 0x31 read/write performs conflict check on selected i/o range. i/o port base 0x60 read/write i/o base [9:8]. address 0x61 read/write i/o base [7:0]. table xi. midi port, logical device number = 3 address register name value type description activate 0x30 read/write activates device. i/o range check 0x31 read/write performs conflict check on selected i/o range. i/o port base 0x60 read/write i/o base [9:8]. address 0x61 read/write i/o base [7:0]. irq level select 0x70 read/write selects interrupt level. irq type select 0x71 read-only active hi, edge-sensi- tive ( not user program- mable). table xii. game port, logical device number = 4 address register name value type description activate 0x30 read/write activates device. i/o range check 0x31 read/write performs conflict check on selected i/o range. i/o port base 0x60 read/write i/o base [9:8]. address 0x61 read/write i/o base [7:0]. table xiii. modem, logical device number = 5 address register name value type description activate 0x30 read/write activates device. i/o range check 0x31 read/write performs conflict check on selected i/o range. i/o port base 0x60 read/write i/o base [9:8]. address 0x61 read/write i/o base [7:0]. irq level select 0x70 read/write selects interrupt level. irq type select 0x71 read only active hi, edge-sensitive (not user programmable). power-down control the ad1812 contains two levels of power-down control. one level of control is accessed through the embedded codec registers and another is accessed via the pnp vendor defined registers. the codec registers allow sections of the embedded codec to be turned off to conserve power.
ad1812 rev. 0 C15C table xiv. codec power-down modes mode powered-down blocks total power down adc, dac, mixer, reference standby adc, dac, mixer mixer power down dac, mixer mixer only adc, dac adc power down adc dac power down dac the registers found in the vendor defined pnp space take prece- dence over any other power-down mode. you can shut down the embedded dsp or the entire codec by writing to these registers. table xv. pnp power-down modes mode powered-down blocks total power down dsp and soundport codec codec control register architecture upon plug and play initialization, a base address is assigned for the windows sound system compatible logical device embed- ded in the ad1812. the ad1812 accepts both data and con- trol information through the 16-bit interface. table xvi. codec direct register map windows sound system address register name base + 0 index address register base + 2 indexed data register base + 4 status register base + 6 pio data registers a write to or a read from the indexed data register will access the indirect register which is selected by the value most recently written to the index address register. the status register and the pio data register are always accessible directly, without in- dexing. the 32 indirect registers are shown in table xvii. table xvii. codec indirect register map windows sound system codec indexed register index reset state left input control 0x00 0x80 right input control 0x01 0x80 left aux #1 input control 0x02 right aux #1 input control 0x03 0x9f left aux #2 input control 0x04 0x9f right aux #2 input control 0x05 0x9f left output control 0x06 0xbf right output control 0x07 0xbf clock and data format 0x08 0x08 interface configuration 0x09 0x00 pin control 0x0a 0x05 test and initialization 0x0b 0x20 miscellaneous information 0x0c 0xca digital mix/attenuation 0x0d 0x00 upper base count 0x0e 0x00 lower base count 0x0f 0x00 alternate feature enable/left mic input control 0x10 0x80 mic mix enable/right mic input control 0x11 0x00 left line gain, attenuate, mute, mix 0x12 0x9f right line gain, attenuate, mute, mix 0x13 0x9f lower timer 0x14 0x00 upper timer 0x15 0x00 upper frequency select 0x16 0x2a lower frequency select 0x17 0xf8 external status 0x18 0x30 revision id 0x19 0x80 mono control 0x1a 0xc0 power-down control 0x1b 0x08 capture data format control 0x1c 0x50 total power-down 0x1d 0x00 capture upper base count 0x1e 0x00 capture lower base count 0x1f 0x00
ad1812 rev. 0 C16C a detailed map of all direct and indirect register contents is summarized for reference as follows: table xviii. codec direct registers (16-bit interface) direct address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wss base res res res res res res res res init mce trd ixa4 ixa3 ixa2 ixa1 ixa0 wss base+2 res res res res res res res res ixd7 ixd6 ixd5 ixd4 ixd3 ixd2 ixd1 ixd0 wss base+4 res res res res res res res res cu/l cl/r crdy sour pu/l pl/r prdy int wss base+6 (read) cd15 cd14 cd13 cd12 cd11 cd10 cd9 cd8 cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0 wss base+6 (write) pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 table xix. codec indirect registers indirect address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 lss1 lss0 lmge res lig3 lig2 lig1 lig0 0x01 rss1 rss0 rmge res rig3 rig2 rig1 rig0 0x02 lmx1 res res lx1a4 lx1a3 lx1a2 lx1a1 lx1a0 0x03 rmx1 res res rx1a4 rx1a3 rx1a2 rx1a1 rx1a0 0x04 lmx2 res res lx2a4 lx2a3 lx2a2 lx2a1 lx2a0 0x05 rmx2 res res rx2a4 rx2a3 rx2a2 rx2a1 rx2a0 0x06 ldm res lda5 lda4 lda3 lda2 lda1 lda0 0x07 rdm res rda5 rda4 rda3 rda2 rda1 rda0 0x08 pfmt1 pfmt0 pc/l ps/m pbsw pinf8 res res 0x09 cpio ppio res res acal sdc cen pen 0x0a xctl1 xctl0 res res res res ien res 0x0b cor pur aci drs orr1 orr0 orl1 orl0 0x0c mid res res res id3 id2 id1 id0 0x0d dma5 dma4 dma3 dma2 dma1 dma0 res dme 0x0e ub7 ub6 ub5 ub4 ub3 ub2 ub1 ub0 0x0f lb7 lb6 lb5 lb4 lb3 lb2 lb1 lb0 0x10 ol te lmg4 lmg3 lmg2 lmg1 lmg0 dacz 0x11 lmme rmme rmg4 rmg3 rmg2 rmg1 rmg0 res 0x12 llm res res llg4 llg3 llg2 llg1 llg0 0x13 rlm res res rlg4 rlg3 rlg2 rllg1 rlg0 0x14 tl7 tl6 tl5 tl4 tl3 tl2 tl1 tl0 0x15 tu7 tu6 tu5 tu4 tu3 tu2 tu1 tu0 0x16 fu7 fu6 fu5 fu4 fu3 fu2 fu1 fu0 0x17 fl7 fl6 fl5 fl4 fl3 fl2 fl1 fl0 0x18 res ti ci pi cu co po p u 0x19 v2 v1 v0 res res cid2 cid1 cid0 0x1a mim mom res res mia3 mia2 mia1 mia0 0x1b adcpwd dacpwd mixpwd res res res res res 0x1c cfmt1 cfmt0 cc/l cs/m cbsw cinf8 res res 0x1d res res res res res res res totpwd 0x1e cub7 cub6 cub5 cub4 cub3 cub2 cub1 cub0 0x1f clb7 clb6 clb5 clb4 clb3 clb2 clb1 clb0 note that the only sticky bit in any of the codec control registers is the interrupt (int) bit. all other bits change with every sample period.
ad1812 rev. 0 C17C system timing and control if the ad1812 is not connected directly to the osc clock on the isa bus, a single fundamental-mode and parallel-tuned 14.31818 mhz crystal oscillator can be substituted to derive all timing parameters. future feature enhanced, pin-compatible versions of the soundport controller will require a 33 mhz clock or crystal input. analog devices suggests developing board layouts that can be easily modified to supply the new clock. data and control transfers the embedded soundport stereo codec supports a dma request/grant architecture for transferring data with the host computer bus. one or two 8-bit or 16-bit dma channels can be supported. programmed i/o (pio) mode is also supported for control register accesses and for applications lacking dma control. pio transfers can be made on one channel while the other is performing dma. transfers to and from the ad1812 are asynchronous relative to the internal data conversion clock. transfers are buffered by fifos located in the capture and playback paths. reference designs and device drivers reference designs and device drivers using the ad1812 are available via bulletin board service. the computer products division runs a bbs that can be reached at speeds up to 14,400 baud, no parity, 8 bits data, 1 stop bit, by dialing (617) 461- 4258. the bbs supports: v.32bis, error correction (v.42 and mnp classes 2, 3, and 4), and data compression (v.42bis and mnp class 5). reference designs can also be found in the ad1812 soundport controller technical reference which can be obtained by contacting your local analog devices sales repre- sentative or authorized distributor. you can also find us on the world wide web at http://www.analog.com. frequency response plots sample frequency ?f s 10 ?0 ?20 0 1.0 0.1 db 0.2 0.4 0.5 0.6 0.7 0.8 0.9 0 ?0 ?00 ?10 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0.3 figure 8. analog-to-digital frequency response to f s (full-scale line-level inputs, C1 db gain) sample frequency ?f s 10 ?0 ?20 0.40 0.44 db 0.48 0.56 0.60 0.64 0.68 0.70 0 ?0 ?00 ?10 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0.52 figure 9. analog-to-digital frequency response transition band (full-scale line-level inputs, C1 db gain) sample frequency ?f s 10 ?0 ?20 0 1.0 0.1 db 0.2 0.4 0.5 0.6 0.7 0.8 0.9 0 ?0 ?00 ?10 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0.3 figure 10. digital-to-analog frequency response to f s (full-scale inputs, 0 db attenuation) sample frequency ?f s 10 ?0 ?20 0.40 0.44 db 0.48 0.56 0.60 0.64 0.68 0.70 0 ?0 ?00 ?10 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0.52 figure 11. digital-to-analog frequency response transition band (full-scale inputs, 0 db attenuation)
ad1812 rev. 0 C18C index page features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ad1812Cspecifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 programmable gain amplifieradc . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 auxiliary, line, microphone and mono input analog gain/amplifiers/attenuators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 digital decimation and interpolation filters . . . . . . . . . . . . . . 2 analog-to-digital converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 digital-to-analog converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 dac attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 digital mix attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 analog output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 system specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 static digital specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 clock specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pqfp & tqfp pin locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 analog signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 modem interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 game port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 midi interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 host pc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 wss compatible codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 sound blaster emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 music synthesizer emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 mpu-401 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 game port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 modem interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 plug and play (pnp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 pnp ad1812 (card) status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 configuration register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 power-down control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 codec control register architecture . . . . . . . . . . . . . . . . . . . . . . . 15 system timing and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 data and control transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 reference designs & device drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 frequency response plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ad1812 rev. 0 C19C outline dimensions dimensions shown in inches and (mm). 160-lead pqfp (s-160) top view (pins down) pin 1 121 160 1 120 41 40 80 81 0.014 (0.35) 0.011 (0.27) 1.239 (31.45) 1.219 (30.95) 1.107 (28.10) 1.100 (27.90) sq sq 0.030 (0.75) 0.022 (0.55) seating plane 0.160 (4.07) max 0.037 (0.95) 0.026 (0.65) 0.004 (0.102) max 0.145 (3.67) 0.125 (3.17) 0.070 (1.77) 0.062 (1.57) 0.070 (1.77) 0.062 (1.57) 10 6 4 4 4 max 160-lead tqfp (st-160) top view (pins down) pin 1 121 160 1 120 41 40 80 81 0.949 (24.10) 0.941 (23.90) sq sq 0.010 (0.25) 0.006 (0.15) 1.031 (26.20) 1.016 (25.80) 0.020 (0.50) bsc seating plane 0.063 (1.60) max 0.030 (0.75) 0.020 (0.50) 0.003 (0.08) max 0.057 (1.45) 0.053 (1.35) 12 typ 6 4 0 5 0.006 (0.15) 0.002 (0.05)
printed in u.s.a. c2100C6C1/96 C20C

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Price & Availability of AD1812JST

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